1. Field of the Invention
The present invention relates to a manufacturing method of active component array substrate. More particularly, the present invention relates to a manufacturing method of thin film transistor array substrate.
2. Description of Related Art
Low temperature poly-silicon thin film transistor (LTPS TFT) overcomes the problem of electron mobility, and furthermore, provides the complementary circuit technology, thus, LTPS TFT has great advantages in device minimization, aperture ratio, image quality and resolution. Besides, presently, the design of LTPS TFT integrates driving circuit into glass, and the increase in system integration further allows the panel has the characteristics of narrow frame size and high image quality. Moreover, LTPS TFT has such advantages as low power consumption, low electromagnetic interference etc., thus, development and improvement in the manufacturing process of LTPS TFT have been highly focused. Below two conventional manufacturing methods of LTPS TFT will be described.
FIGS. 1A˜1E are diagrams illustrating a conventional manufacturing flow of a LTPS TFT array substrate. Referring to FIG. 1A first, the conventional manufacturing method of LTPS TFT array substrate includes following steps. First, a array region 110b. Next, a buffer layer 120 is formed on the substrate 110. After that, a plurality of first poly-silicon islands 130a, a plurality of second poly-silicon islands 130b, and a plurality of third poly-silicon islands 130c are formed on the buffer layer 120. Wherein, the first and the second poly-silicon islands 130a and 130b are disposed on the peripheral region 110a and the third poly-silicon islands 130c are disposed on the array region 110b. A patterned photoresist layer 210 is formed above the substrate 110 to cover the first poly-silicon islands 130a. Then, a channel doping process S110 is performed to the second and the third poly-silicon islands 130b and 130c with the patterned photoresist layer 210 as mask. Next, the patterned photoresist layer 210 is removed.
Referring to FIG. 1B, a patterned photoresist layer 220b is formed above the substrate 110 to cover the first poly-silicon islands 130a and portions of the second and the third poly-silicon islands 130b and 130c. Then, a second ion implantation process S120b is performed to the second and the third poly-silicon islands 130b and 130c with the patterned photoresist layer 220b as mask, so as to form a second source/drain 132b in each of the second poly-silicon islands 130b and a third source/drain 132c in each of the third poly-silicon islands 130c. In addition, a second channel region 134b is between each second source/drain 132b, and a third channel region 134c is between each third source/drain 132c. Next, the patterned photoresist layer 220b is removed.
Referring to FIG. 1C, a gate insulating layer 140 is formed on the buffer layer 120 to cover the first, the second, and the third poly-silicon islands 130a, 130b, and 130c. Next, a plurality of first gates 150a, a plurality of second gates 150b, a plurality of third gates 150c, and a plurality of capacitance electrodes 150d are formed on the gate insulating layer 140. After that, a lightly doped drain ion implantation process S130 is performed to the second and the third poly-silicon islands 130b and 130c to form a plurality of second lightly doped drains 136b and a plurality of third lightly doped drains 136c. 
Referring to FIG. 1D, a patterned photoresist layer 220a is formed above the substrate 110 to cover the second and the third poly-silicon islands 130b and 130c. Next, a first ion implantation process S120a is performed to the first poly-silicon islands 130a to form a plurality of first sources/drains 132a. Besides, a first channel region 134a is between each first source/drain 132a. Next, the patterned photoresist layer 220a is removed.
Referring to FIG. 1E, a first patterned passivation layer 160 is formed on the gate insulating layer 140 and which exposes portions of each of the first sources/drains 132a, portions of each of the second sources/drains 132b, and portions of each of the third sources/drains 132c. Next, a plurality of first source/drain conductive layers 170a, a plurality of second source/drain conductive layers 170b, and a plurality of third source/drain conductive layers 170c are formed on the first patterned passivation layer 160. Wherein, each of the first source/drain conductive layers 170a is electrically connected to the first source/drain 132a, and each of the second source/drain conductive layers 170b is electrically connected to the second source/drain 132a. In addition, each of the third source/drain conductive layers 170c is electrically connected to the third source/drain 132c. 
Next, a second patterned passivation layer 180 is formed on the first patterned passivation layer 160 and which exposes portions of the third source/drain conductive layers 170c. After that, a plurality of pixel electrodes 190 is formed on the second patterned passivation layer 180 and each pixel electrode is electrically connected to the corresponding third source/drain conductive layer 170c. Here the conventional manufacturing flow of the LTPS TFT array substrate 100 is about completed. Below another conventional manufacturing method of LTPS TFT array substrate will be described.
FIGS. 2A˜2E are diagrams illustrating another conventional manufacturing flow of a LTPS TFT array substrate. Referring to FIGS. 2A˜2B, the content of FIGS. 2A˜2B is approximately the same as that of FIGS. 1A˜1B. In short, the buffer layer 120, the first poly-silicon islands 130a, the second poly-silicon islands 130b, the third poly-silicon islands 130c, the channel doping process S110, and the second ion implantation process S120b are completed on the substrate 110 in sequence.
Referring to FIG. 2C, a gate insulating layer 140 is formed on the buffer layer 120 and which covers the first, the second, and the third poly-silicon islands 130a, 130b, and 130c. Then, a patterned conductive material layer 150 and a plurality of first gates 150a are formed on the gate insulating layer 140. The patterned conductive material layer 150 covers the second poly-silicon islands 130b and the third poly-silicon islands 130c. Next, a first ion implantation process S120a is performed to the first poly-silicon islands 130a with the first gates 150a as mask to form a plurality of first sources/drains 132a. Besides, a first channel region 134a is between each of the first sources/drains 132a. 
Referring to FIG. 2D, a patterned metal layer 150 is patterned to form a plurality of second gates 150b, a plurality of third gates 150c, and a plurality of capacitance electrodes 150d. Next, a lightly doped drain ion implantation process S130 is performed to form a plurality of second lightly doped drains 136b and a plurality of third lightly doped drains 136c. 
Refer to FIG. 2E, whose content is similar to that of FIG. 1E. In short, after performing the lightly doped drain ion implantation process S130, the first patterned passivation layer 160, the first source/drain conductive layers 170a, the second source/drain conductive layers 170b, the third source/drain conductive layers 170c, the second patterned passivation layer 180, and the pixel electrode 190 are formed in sequence to complete the conventional manufacturing process of LTPS TFT array substrate 100.
LTPS TFT array substrate has advantages such as high aperture ratio and narrow frame size since the driving circuit is integrated to the glass substrate. However, compared to the 5 photo mask processes of typical amorphous silicon TFT (a-Si TFT) array substrate, the 9 photo mask processes of LTPS TFT array substrate is more complex. Accordingly, it is difficult to increase the panel size of the conventional manufacturing process of LTPS TFT array substrate and to control product qualified rate, which may further cause the problem of high manufacturing cost.